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- Nothing.
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- Processor cycles
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- Number of instructions completed.
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- RTCSELECT bit transition. 0 = 47, 1 = 51, 2 = 55, 3 = 63 bits from the time base lower register.
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- Number of instructions dispatched
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- Number of cycles a load miss takes
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- Data cache misses (data cache line fill)
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- Number of itlb misses
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- Number of branches completed. Indicates the number of branch instructions completed every cycle.
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- Number of reservations successfully obtained
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- Number of mfspr instructions dispatched (speculative)
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- Number of icbi instructions. The icbi instruction may not hit in the cache.
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- Number of pipeline-flushing operations (sc, isync, mtspr[xer], floating-point operations with divide
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- Branch unit produced result (branch or CR-logical instruction finished)
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- SCIU0 unit produced result (add, subtract, compare, rotate, shift, or logical instruction)
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- MCIU unit produced result (multiply/divide or SPR instruction)
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- Number of instructions dispatched to the branch unit
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- Number of instructions dispatched to the SCIU0 unit
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- Number of loads completed.
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- Number of instructions dispatched to the MCIU
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- Number of snoop hits occurred
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